In a microprogrammed computer, sequences of microinstructions are used to emulate higher level macroinstructions. After a macroinstruction is fetched, some technique must be used to vector the computer to the microaddress where the microinstruction sequence for that macroinstruction starts. Once vectored, the microinstruction sequence can then be accessed and executed.
This function of vectoring the computer to the microinstruction sequence is generally performed via a jump table PROM in the prior art. When such is the case, part or all of the macroinstruction opcode is used to address the jump table. The data stored in the PROM at the address location corresponding to the opcode is then used as the address of the first microinstruction of the emulation code.
For many systems in the prior art, it takes one or more microcycles to generate the microaddress once the macroinstruction opcode is available, and it takes still another microcycle to read the microinstruction from control store after the microaddress is available. Thus there is a minimum of two microcycles from the time that a macroinstruction is available to the time that the first microinstruction of the emulation sequence is available. Furthermore, due to limitations in PROM size and density, hitherto it has never been feasible to decode an entire 16-bit macroinstruction opcode in one microcycle. To overcome this limitation, additional decoding is often done using vectored jumps in microcode, or additional levels of jump tables. Thus, part of the macroinstruction opcode is vectored to one microinstruction sequence during one cycle, and another part is vectored to another microinstruction sequence in another cycle. In short, multiple microcycles are needed to complete a decoding process in the prior art. FIG. 1, depicting a typical prior art vectoring scheme, clearly shows that the fetching and accessing of a microinstruction sequence for execution necessitate a minimum of two microcycles.